The present invention relates to an integrated circuit device including a scan test circuit, a method of testing the integrated circuit device, a database for use in design of the integrated circuit device and a method of designing the integrated circuit device.
An integrated circuit device, such as a system LSI, including a large number of circuits as well as a scan test circuit for testing these circuits is conventionally known.
FIG. 13 is a perspective view for illustrating a state of designing an integrated circuit device in which data of circuits to be designed are taken out from a data base. Data of the respective circuits are registered in the database as a core 1, a core 2, a core 3 and a core 4, which are taken out from the database to be appropriately arranged in the integrated circuit device. As the data of these cores, data previously used may be reused or new data may be created.
Although not shown in FIG. 13, some integrated circuit devices include a scan test circuit for testing each logic circuit included therein. In a scan test method, flip-flops included in the integrated circuit device are used to test, for example, whether or not each element (a logic circuit, in particular) of the integrated circuit device is normally operated. These flip-flops are connected to one another, so as to form a scan test circuit working as a shift register in a test mode. An input/output pin of the integrated circuit device is used as a shift input/output terminal, so that the internal flip-flops can be accessed from the outside. In this method, an internal logic circuit can be dealt with as a combinational circuit, and thus, a self-diagnostic function can be realized. In this case, a combinational circuit means a circuit including merely an element not conducting a storage operation, such as an AND, an OR and a gate.
FIG. 14(a) is a diagram for showing part of a conventional system LSI including a scan test circuit. As is shown in FIG. 14(a), between a combinational circuit 110 and another combinational circuit 110, that is, internal circuits of the system LSI, flip-flops 111A through 111F used for the scan test are disposed so as to be connected to each combinational circuit 110. Although merely one combinational circuit 110 is shown in FIG. 14(a), the system LSI actually includes a large number of combinational circuits, between which flip-flops for forming a scan test circuit are disposed.
Each flip-flop 111 has a terminal D for bringing in a data signal, a terminal DT for bringing in a scan test signal, a clock terminal for bringing in a clock signal, a terminal NT for bringing in a signal NT for setting an operation mode, and a terminal Q for outputting the scan test signal and the data signal. (Although not shown in the drawing, a general flip-flop additionally has a terminal/Q.)
The terminal Q of one flip-flop (for example, 111A) is connected to the terminal DT of an adjacent flip-flop (for example, 111B), so that a scan test circuit can be formed by serially connecting all the flip-flops 111A through 111F together. A scan-in signal input from an input pin, serving as a scan test signal input terminal, of the system LSI is received at the terminal DT of a flip-flop disposed at the top of one scan test circuit within the system LSI, and a scan-out signal is output from the terminal Q of a flip-flop at the last stage of the scan test circuit to the outside through an output pin of the system LSI. In general, on e system LSI includes several through dozens of scan test circuits.
In testing the system LSI, the input pin of the system LSI serving as the scan test signal input terminal and the output pin thereof serving as the scan test output terminal are connected to a tester, so as to receive the scan test signal DT output from the tester at the scan test signal input terminal and to send the data signal D having passed through the combinational circuit of the system LSI (namely, a data value obtained from the scan test signal having passed through the combinational circuit) to the tester. The tester compares the value of the data signal D with an expected value, thereby determining whether or not each element of the combinational circuit 110 is defective.
In this test of the system LSI using the tester, the signal NT is switched to enter the test mode. In particular, the test mode for the scan test is classified into a shift mode and a capture mode.
FIG. 14(b) is a diagram for showing change with time of control during the scan test. While the signal NT is in the shift mode, the scan test signal DT is supplied to the flip-flops 111A through 111F. In other words, the scan test signal is successively sent from the terminal Q of one flip-flop to the terminal DT of another flip-flop at the next stage every clock, so that all the flip-flops constituting the scan test circuit can hold the scan test signal to be input to the combinational circuit. This takes time corresponding to the number of clocks (which is several hundred clocks or more in general) equal to the number of flip-flops included in the scan test circuit (namely, time corresponding to several hundred clock periods or more). With the scan test signal DT held by the flip-flops 111A through 111F, the signal NT is switched to enter the capture mode, so that each of the flip-flops 111A through 111F can fetch the data signal. In this case, the flip-flops 111A through 111F simultaneously fetch the data signal, and hence, the capture operation takes time corresponding to one clock. The data signal D is a signal having passed through the combinational circuit 110, and has an output value corresponding to the value of the scan test signal DT having been input to the combinational circuit 110. Then, in a subsequent test mode, a next scan test signal DT is sent to the flip-flops 111A through 111F, and at the same time, the data signals D held by the flip-flops 111A through 111F are sent from the output pin to the tester. When the shift operation is completed, each of the flip-flops 111A through 111F included in the scan test circuit holds the scan test signal DT instead of the data signal D fetched in the capture mode. Thereafter, the capture mode and the shift mode are alternately repeated.
In this manner, by comparing an expected value, which is expected to be obtained by allowing the scan test signal DT input to the combinational circuit 110 to pass through the combinational circuit, with the data signal D actually output from the combinational circuit 110, it can be determined whether or not the combinational circuit 110 is defective.
In conducting the scan test, it is necessary to simultaneously operate as many combinational circuits as possible so as to complete the scan test of the integrated circuit device in a short period of time. This is because, when the tester is used for a long period of time, the cost of the integrated circuit device ultimately becomes high due to high running cost of the tester.
Therefore, in general, in sending a scan test signal to the flip-flops, test patterns in accordance with the number of flip-flops are respectively shifted by the number of clocks equal to the number of the flip-flops, and then the capture operation is started after one clock.
When a large number of cores are operated in a short period of time as in the aforementioned scan test of the integrated circuit device, however, the momentary power consumption (peak power consumption) during the test can be very large. Particularly, since a large number of and a variety of circuits are recently packed in one chip of an integrated circuit device such as a system LSI, the peak power consumption is estimated to be extremely large.
FIG. 15 is a diagram for exemplifying change with time of power consumption in the entire integrated circuit device during the scan test. As is shown in FIG. 15, the power consumption during the test is momentarily increased by operating the cores 1 through 4 simultaneously (namely, in one clock period). Although power supply is generally designed wit h respect to power consumption during general use of a device, the power supply design does not take the increase of peak power consumption during the test into consideration. In general use, there is substantially no chance that all the circuits included in an integrated circuit device are simultaneously operated, and hence, the peak power consumption during general use is not very large. As a result, an integrated circuit device designed without considering the peak power consumption during the test cannot be normally operated in the scan test or can be damaged by the test.
An object of the invention is reducing the peak power consumption in a scan test by providing means for dispersing operation timing of respective circuits of an integrated circuit device in the scan test while suppressing increase of time of using a tester.
The first integrated circuit device of this invention comprises plural logic circuits and plural flip-flop circuits disposed between the plural logic circuits, and each of the flip-flop circuits includes a first input port for receiving a scan test signal; a second input port connected to corresponding one of the logic circuits for receiving, as a data signal, an output of the logic circuit according to a scan test signal input to the logic circuit; a third input port for receiving a control signal for switching input to the flip-flop circuit between the scan test signal and the data signal; a fourth input port for receiving a hold signal; a first output port connected to the logic circuit for transferring the scan test signal to the logic circuit; and a second output port for outputting the data signal and the scan test signal, a scan test circuit is formed by serially connecting the plural flip-flop circuits by successively connecting the second output port of an arbitrary flip-flop circuit among the plural flip-flop circuits to the first input port of another of the flip-flop circuits disposed at a next stage, and an output value output from the first output port is fixed in receiving the hold signal at the fourth input port.
Accordingly, in the shift operation of the scan test, the internal state of the logic circuit is prevented from changing in accordance with every clock of the shift operation. As a result, the peak power consumption during the scan test of the integrated circuit device can be reduced.
In the first integrated circuit device, the output value output from the first output port of each of the flip-flop circuits can be fixed to a value held in receiving the hold signal.
In this case, the fourth input port of each of the flip-flop circuits may also work as the third input port.
Alternatively, in the first integrated circuit device, the output value output from the first output port of each of the flip-flop circuits can be fixed to 1 or 0 regardless of a value held in receiving the hold signal.
The second integrated circuit device of this invention comprises first and second circuits; a first test circuit for testing the first circuit; a second test circuit for testing the second circuit; a clock supply part for supplying a clock signal to the first circuit and the second circuit; a clock inverting part for inverting the clock signal supplied from the clock supply part and outputting an inverted clock signal; and an output switching circuit disposed between the clock inverting part and the second circuit for receiving the clock signal and the inverted clock signal and outputting the inverted clock signal to the second circuit in testing the second circuit.
Accordingly, even when the test is performed simultaneously in plural circuits, the operation timing is shifted by a half clock period, and hence, increase of the peak power consumption due to the simultaneous test of the plural circuits can be avoided.
In the second integrated circuit device, the first circuit can be a logic circuit, and the second circuit can be a memory.
The first method of this invention of testing an integrated circuit device, including plural logic circuits and plural flip-flop circuits disposed between the logic circuits, the flip-flop circuits being successively connected to form a scan test circuit, conducts a scan test by repeating the steps of (a) conducting a holding operation for fixing an output signal from each of the flip-flop circuits to a path connected to corresponding one of the logic circuits; (b) conducting a shift operation for successively sending a scan test signal to the flip-flop circuits and for successively sending a data signal from each of the flip-flop circuits to outside of the integrated circuit device; (c) conducting a hold releasing operation for releasing the output signal fixed in the step (a) after completing the shift operation; and (d) conducting a capture operation for capturing an output signal of the logic circuit by each of the flip-flop circuits after the step (c).
According to this method, it is possible to suppress increase of the peak power consumption derived from change of the internal state of the logic circuit in accordance with the scan test signal during the shift operation. Furthermore, the peak power consumption during a holding operation, a hold releasing operation and a capture operation can be reduced by additionally conducting the following procedures:
With elements of each of the logic circuits divided into plural groups, the output signal can be fixed to a value held by the flip-flop circuit in fixing the output signal in the step (a), the step (c) can be conducted with respect to each of the groups, and after completing a first shift operation, the step (a) can be carried out after the step (c) and before the step (d).
With elements of each of the logic circuits divided into plural groups, the output signal can be fixed to a value held by the flip-flop circuit in fixing the output signal in the step (a), the step (c) and the step (d) can be carried out with respect to each of the groups in a manner that a capture operation of one group is carried out after a hold releasing operation of the group, and after completing a first shift operation, the step (a) can be carried out after the step (d).
With elements of each of the logic circuits divided into plural groups, the output signal can be fixed to 1 or 0 regardless of a value held by the flip-flop circuit in fixing the output signal with respect to each of the groups in the step (a), the step (c) and the step (d) can be carried out with respect to each of the groups in a manner that a capture operation of one group is carried out after a hold releasing operation of the group, and after a second shift operation, the step (a) can be carried out after the step (d).
In the first method of testing an integrated circuit device, elements of each of the logic circuits are divided into groups preferably in a manner that peak power consumption during the scan test does not exceed an allowable value of power consumption of the integrated circuit device in general use.
In the second method of this invention of testing an integrated circuit device including first and second circuits, a first test circuit for testing the first circuit, a second test circuit for testing the second circuit and a clock supply part for supplying a clock signal to the first and second circuits, the first circuit is tested in accordance with the clock signal, and the second circuit is tested, while the first circuit is being tested, in accordance with an inverted clock signal obtained by inverting the clock signal.
According to this method, even when plural circuits are simultaneously tested, the increase of the peak power consumption can be suppressed.
In the case where, in the second method of testing an integrated circuit device, the first circuit is a logic circuit and the second circuit is a memory, remarkable effects can be exhibited.
In the method of this invention of designing an integrated circuit device using a database including at least one core storing data necessary for designing the integrated circuit device, estimated information regarding power consumption during a test of the core is described in the database, the estimated information regarding power consumption during a test of the core is used in selecting the core in higher level design, and design information obtained as a result of the higher level design is used in lower level design.
According to this method, repeat of re-design loop can be reduced and a circuit can be more rapidly designed as compared with the case where power consumption is first estimated in the lower level design.
In the method of designing an integrated circuit device, design using the estimated information is preferably architecture design.
Furthermore, the design information preferably includes information for instructing, by using information of data flow among plural cores designed in the architecture design, to divide the cores into plural groups and to design a circuit structure capable of conducting a capture operation successively in the order from a group on a lower level side of the data flow.
In the method of designing an integrated circuit device, the design information preferably includes information on grouping for dividing the core into plural groups.
In the method of designing an integrated circuit device, the design information preferably includes information on a test method.
In the method of designing an integrated circuit device, when the database includes plural cores requiring different test methods, the design information preferably includes test scheduling determined, with each of the test methods represented by a plane test pattern obtained by using time and a pin number as a coordinate, so as to minimize test time in consideration of restriction in a number of usable pins and not to allow peak power consumption to exceed an allowable value of power consumption of the integrated circuit device in general use.
The database of this invention for use in design of an integrated circuit device comprises plural cores each storing data necessary for designing the integrated circuit device, and the database includes information regarding power consumption of the cores during a test.
Accordingly, an integrated circuit device can be designed in consideration of not only power consumption during general use but also power consumption during a test.
The information regarding power consumption during a test includes an estimated value of peak power consumption of each of the cores; an estimated maximum transition number of states of each of the cores, a circuit scale of each of the cores and power consumption of gates included in each of the cores; and a circuit and a simulation pattern.
In the database for use in design of an integrated circuit device, the database preferably includes information regarding a possible division number of each of the cores. The information regarding a possible division number of each of the cores includes a level at which power consumption during a shift operation is equal to peak power consumption in dividing the core; a division number and power consumption of a core not accompanied by change in a test or design; and a division number and peak power consumption in every clock of a core not accompanied by change in a test or design.
Furthermore, the database preferably includes information regarding division probability of each of the cores. The information regarding division probability of each of the cores includes a maximum possible division number of the core and a number of clock systems.